A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., FPGA, CPLD), including both high-end and commodity variations.
Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit. Abstracted from Chapter 4 of . In those multi-core systems, rarely used resources can be shared between all the cores in a cluster.
While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a multi-core processor. The number of soft processors on a single FPGA is limited only by the size of the FPGA. Some people have put dozens or hundreds of soft microprocessors on a single FPGA.Presented at the 8th International Workshop on Field-Programmable Logic and Applications (FPL'98), held in Tallinn, Estonia, August 31 to September 3, 1998. This is one way to implement massive parallelism in computing and can likewise be applied to in-memory computing.
A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.
Core comparison
Processor Developer Open source Bus support Notes Project home Description language based on the ARM instruction set architecture Amber Conor Santifort Wishbone ARMv2a 3-stage or 5-stage pipelinehttps://opencores.org/project/amber Verilog Cortex-M1 ARM http://www.arm.com/products/system-ip/interconnect/index.php 70–200MHz, 32-bit RISC http://www.arm.com/products/CPUs/ARM_Cortex-M1.html Verilog based on the AVR instruction set architecture Navré Sébastien Bourdeauducq Direct SRAM Atmel AVR-compatible 8-bit RISC http://opencores.org/project,navre Verilog pAVR Doru Cuturela Atmel AVR-compatible 8-bit RISC http://opencores.org/project,pavr VHDL softavrcore Andras Pal Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM) Atmel AVR-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included http://opencores.org/project/softavrcore Verilog based on the MicroBlaze instruction set architecture AEMB Shawn Tan Wishbone MicroBlaze EDK 3.2 compatible http://www.aeste.my/aemb Verilog MicroBlaze Xilinx PLB, OPB, FSL, LMB, AXI4 https://web.archive.org/web/20030430214925/http://www.xilinx.com/microblaze/ OpenFire Virginia Tech CCM Lab OPB, FSL Binary compatible with the MicroBlaze https://web.archive.org/web/20090724052731/http://www.ccm.ece.vt.edu/~scraven/openfire.html, http://opencores.org/project,openfire_core,overview Verilog SecretBlaze LIRMM, University of Montpellier / CNRS Wishbone MicroBlaze ISA, VHDL http://www.lirmm.fr/ADAC/?page_id=462 VHDL based on the MCS-51 instruction set architecture MCL51 MicroCore Labs Ultra-small-footprint microsequencer-based 8051 core 312 Artix-7 LUTs. Quad-core 8051 version is 1227 LUTs. http://www.microcorelabs.com TSK51/52 Altium Wishbone / Intel 8051 8-bit Intel 8051 instruction set compatible, lower clock cycle alternative https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design, https://web.archive.org/web/20131008041359/http://wiki.altium.com/display/ADOH/TSK51x+MCU based on the MIPS instruction set architecture BERI University of Cambridge MIPS http://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Bluespec Dossmatik René Doss Pipelined bus MIPS I instruction set pipeline stages http://www.dossmatik.de/mais-cpu.html VHDL TSK3000A Altium Wishbone 32-bit R3000-style RISC modified Harvard architecture CPU https://web.archive.org/web/20131020113429/http://wiki.altium.com/display/ADOH/TSK3000A based on the PicoBlaze instruction set architecture PacoBlaze Pablo Bleyer Compatible with the PicoBlaze processors http://bleyer.org/pacoblaze Verilog PicoBlaze Xilinx https://web.archive.org/web/20030501203653/http://www.xilinx.com/picoblaze/ VHDL, Verilog based on the RISC-V instruction set architecture f32c University of Zagreb AXI, SDRAM, SRAM 32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain https://github.com/f32c/f32c VHDL NEORV32 Stephan Nolting Wishbone b4, AXI4 rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain https://github.com/stnolting/neorv32, https://opencores.org/projects/neorv32 VHDL VexRiscv SpinalHDL AXI4 / Avalon 32-bit, RISC-V, up to 340MHz on Artix 7. Up to 1.44DMIPS/MHz. https://github.com/SpinalHDL/VexRiscv VHDLVerilog (SpinalHDL) based on the SPARC instruction set architecture LEON2(-FT) ESA AMBA2 SPARC V8 http://www.esa.int/TEC/Microelectronics/SEMUD70CYTE_0.html VHDL LEON3/4 Aeroflex Gaisler AMBA2 SPARC V8 http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=156&Itemid=104 VHDL OpenPiton Princeton Parallel Group Manycore SPARC V9 http://parallel.princeton.edu/openpiton/specs.html Verilog OpenSPARC T1 Sun 64-bit http://www.opensparc.net/opensparc-t1/index.html Verilog Tacus/PIPE5 TemLib Pipelined bus SPARC V8 http://temlib.org VHDL based on the x86 instruction set architecture CPU86 HT-Lab 8088-compatible CPU in VHDL http://www.ht-lab.com/cpu86.htm VHDL MCL86 MicroCore Labs 8088 BIU provided. Others easy to create. Cycle accurate 8088/8086 implemented with a microsequencer. Less than 2% utilization of Kintex-7. http://www.microcorelabs.com s80x86 Jamie Iles Custom 80186-compatible GPLv3 core https://www.jamieiles.com/80186/ SystemVerilog Zet Zeus Gómez Marmolejo Wishbone x86 PC clone https://web.archive.org/web/20130215004406/http://zet.aluzina.org/index.php/Zet_processor Verilog ao486 Aleksander Osman Avalon i486SX compatible core https://github.com/alfikpl/ao486 Verilog based on the PowerPC/Power instruction set architecture PowerPC 405S IBM CoreConnect 32-bit PowerPC v.2.03 Book E Verilog PowerPC 440S IBM CoreConnect 32-bit PowerPC v.2.03 Book E Verilog PowerPC 470S IBM CoreConnect 32-bit PowerPC v.2.05 Book E Verilog Microwatt IBM/OpenPOWER Wishbone 64-bit PowerISA 3.0 proof of concept https://github.com/antonblanchard/microwatt VHDL Chiselwatt IBM/OpenPOWER Wishbone 64-bit PowerISA 3.0 https://github.com/antonblanchard/chiselwatt Chisel Libre-SOC Libre-SoC.org Wishbone 64-bit PowerISA 3.0. CPU/GPU/VPU implementation and custom vector instructions https://libre-soc.org Python/nMigen A2I IBM/OpenPOWER Custom PBus 64-bit PowerPC 2.6 Book E. In order core https://github.com/openpower-cores/a2i VHDL A2O IBM/OpenPOWER Custom PBus 64-bit PowerPC 2.7 Book E. Out of order core https://github.com/openpower-cores/a2o Verilog Other architectures ARC ARC International, Synopsys 16/32/64-bit ISA RISC https://www.synopsys.com/designware-ip/processor-solutions.html Verilog ERIC5 Entner Electronics 9-bit RISC, very small size, C-programmable https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html VHDL H2 CPU Richard James Howe Custom 16-bit stack machine, designed to execute Forth directly, small https://github.com/howerj/forth-cpu VHDL Instant SoC FPGA Cores Custom 32-bit RISC-V M Extension, SoC defined by C++ http://www.fpga-cores.com/instant-soc/ VHDL JOP Martin Schoeberl SimpCon / Wishbone (extension) Stack-oriented, hard real-time support, executing Java bytecode directly https://web.archive.org/web/20190417225405/http://www.jopdesign.com/ VHDL LatticeMico8 Lattice Wishbone http://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/Mico8.aspx Verilog LatticeMico32 Lattice Wishbone http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm Verilog LXP32 Alex Kuznetsov Wishbone 32-bit, 3-stage pipeline, register file based on block RAM https://lxp32.github.io/ VHDL MCL65 MicroCore Labs Ultra-small-footprint microsequencer-based 6502 core 252 Spartan-7 LUTs. Clock cycle-exact. https://github.com/MicroCoreLabs/Projects MRISC32-A1 Marcus Geelnard Wishbone, B4/pipelined 32-bit RISC/Vector CPU implementing the MRISC32 ISA https://mrisc32.bitsnbites.eu/ VHDL NEO430 Stephan Nolting Wishbone (Avalon, AXI4-Lite) 16-bit MSP430 ISA-compatible, very small size, many peripherals, highly customizable https://github.com/stnolting/neo430 VHDL Nios, Nios II Altera Avalon https://web.archive.org/web/20101225092752/http://www.altera.com/products/ip/processors/nios2/ni2-index.html Verilog OpenRISC OpenCores Wishbone 32-bit; done in ASIC, Actel, Altera, Xilinx FPGA. https://openrisc.io/ Verilog SpartanMC TU Darmstadt / TU Dresden Custom (AXI support in development) 18-bit ISA (GNU Binutils / GCC support in development) http://www.spartanmc.de Verilog SYNPIC12 Miguel Angel Ajo Pelayo PIC12F compatible, program synthesised in gates http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core VHDL xr16 Jan Gray XSOC abstract bus 16-bit RISC CPU and SoC featured in Circuit Cellar Magazine #116-118 http://www.fpgacpu.org/xsoc/index.html Schematic YASEP Yann Guidon Direct SRAM 16 or 32 bits, RTL in VHDL & asm in JS, microcontroller subset : ready http://yasep.org, https://web.archive.org/web/20121207045204/http://yasep.org/VHDL/, http://yasep.org/#!ASM/impASM#examples/keywords.yas VHDL ZipCPU Gisselquist Technology Wishbone, B4/pipelined 32-bit CPU targeted for minimal FPGA resource usage http://zipcpu.com/about/zipcpu.html, http://zipcpu.com/about/gisselquist-technology.html Verilog ZPU Zylin AS Wishbone Stack based CPU, configurable 16/32 bit datapath, eCos support http://opensource.zylin.com/zpu.htm VHDLRISC5 Niklaus Wirth CustomRunning a complete graphical Oberon System including an editor and compiler. Software can be developed and ran on the same FPGA board.http://www.projectoberon.com/Verilog
See also Network-on-a-chip (NoC) Reconfigurable computing Hardware acceleration CPU simulator
References
External links Soft CPU Cores for FPGA Detailed Comparison of 12 Soft Microprocessors FPGA CPU News Freedom CPU website Microprocessor cores on Opencores.org (Expand the "Processor" tab) NikTech 32 bit RISC Microprocessor MANIK.